| High performance at low cost is a requirement of many cutting edge applications from areas such as signal processing, graphics, and communications. Some examples include motion estimation for real-time video encoding and accurate low-power filtering for wireless communications. These applications not only demand good cost/performance but also high flexibility in order to support multiple standards, changing algorithms, and the ever increasing short time-to-market. Unfortunately, today's implementation alternatives either give up flexibility for good cost/performance (full custom designs) or provide a tremendous amount of flexibility at the expense cost and performance (microprocessors and DSPs). To address this problem, this dissertation introduces reconfigurable pipelined datapaths (RaPiD), a new architecture style for compute-intensive applications that bridges the cost/performance gap between general-purpose and application specific architectures.; A RaPiD architecture is optimized for highly repetitive, compute-intensive tasks that are abundant in the nested-loop kernels of many applications. Deep application-specific computation pipelines are configured in RaPiD that deliver very high performance for a wide range of applications. RaPiD achieves this using a coarse-grained reconfigurable architecture that mixes the appropriate amount of static configuration with dynamic control. RaPiD architectures provide significantly higher performance than general-purpose processors on a wide range of applications. Moreover, RaPiD architectures provide the flexibility that application-specific architectures can't provide.; This thesis develops an integrated architecture, language, and compiler for reconfigurable pipelined datapaths. The fundamental features of a RaPiD architecture are developed, including the configurable datapath and the configurable instruction decoder. Speed, area, and power estimates are provided for a benchmark architecture targeting signal processing applications. In addition, a programming language for deeply pipelined, parallel computations is presented, as well as a compiler that extracts a program's datapath, control, and I/O and efficiently maps the results to the architecture. Finally, this thesis presents performance numbers for several applications and evaluates how the benchmark architecture fills the cost/performance gap between general-purpose processors and ASICs on a specific set of computations. |
