A reconfigurable systolic array architecture for multicarrier wireless applications

Multicarrier (MC) wireless communication technologies depend heavily on efficient realization of digital signal processing functions. For high data rate communication, these DSP functions must be realized by means of parallel signal processing techniques. Fortunately, the principal DSP building blocks for MC communications such as DFTs and FIR filter banks lend themselves readily to parallel processing architectures. However, the realization of MC communication and MC circuitry within a Cognitive Radio (CR) platform or Software Defined Radio (SDR) may impose further requirements on the DSP portion namely reconfigurability. In terms of these DSP building blocks, the reconfigurable nature of the circuits could for example involve changes to: dimensionality, functionality, as well as, filter coefficient and "twiddle factor" values.;The RSA is a homogeneous, coarse-grained and regular architecture where each reconfigurable Processing Element (PE) is connected to its nearest neighbours. The RSA's homogeneous and regular characteristics facilitate circuit expansion to support applications that require higher data throughput performance. These characteristics also enable the circuit to support scalable computations for large data path applications within the constraint of available hardware resources. The RSA's regular characteristics also facilitate reconfiguration of Polyphase filter circuits for different number of channels and different number of taps.;The DFT circuit implementations are based on a novel algorithmic technique introduced to reduce the overall number of vector-matrix products to be mapped on the RSA arrays. The proposed technique enables the RSA-based DFT/IDFT circuits to support computations for N-point input sequence where N is not restricted to a power of two.;Novel multiplier design techniques have been proposed and applied to the implementation of multipliers in the PE cell. Comparison results for multiplier designs based on the proposed technique against circuits designed using existing techniques show that the proposed designs offer higher throughput performance and require less hardware than the latter.;This dissertation outlines the design, simulation and circuit implementation of a new dynamically reconfigurable systolic array (RSA) architecture that is capable of supporting a wide range of simple and complex DSP functions for MC wireless applications. The RSA architecture presented here supports the computations of Polyphase filters, IDFT/DFTs, and IDFT-Polyphase/Polyphase-DFT for input signals consisting of N channels. The IDFT-Polyphase and Polyphase-DFT functions are usually employed to perform up and down conversion of composite FDM signals. A circuit that supports dynamic reconfiguration of IDFT-Polyphase/Polyphase-DFT functions could be used for the up/down conversion of FDM signals consisting of different number of subcarriers or channel bandwidths according to requirements.