A CMOS Direct-RF Sampling Band-Pass SigmaDelta Receiver with Integrated QPLL for Software-Defined Radio Applications

A direct-RF-sampled band-pass SigmaDelta modulator enables reconfigurable RF A/D conversion. It features a programmable narrow-band Q-enhanced low-noise amplifier and a phase-locked loop implemented using a low-phase-noise injection-locked harmonic-filtering quadrature voltage-controlled oscillator. The quadrature outputs of the PLL provide phase synchronization between a raised-cosine DAC and the quantizer. The three-tap raised-cosine finite-impulse response filter is embedded in the RF DAC. A complete receiver demonstrates progress towards Software-Defined Radio (SDR) applications. Implemented in 0.13 mum CMOS, it consumes 41 mW and achieves a spur-free dynamic range (SFDR) of 52/42 dB when tuned from 0.8/2.1 GHz. Measured IIP3 varies from -5 dBm to -7 dBm over the realized tuning range. For the PLL, the phase noise is -113 dBc/Hz at a 1 MHz offset, the carrier reference spur is at -74.5dBc, and the RMS period jitter is 1.38 ps at 3.2 GHz. The technique is also applicable to multi-channel parallel RF A/D conversion applications.;To further exploit the digital processing capability available in modern CMOS technology, we also investigate the use of power efficient architectural schemes for digital calibration of low-pass SigmaDelta ADCs. Conventional full-rate least-mean squares (LMS) calibration techniques are limited from slow convergence and increased computational complexity/power dissipation especially for higher sampling frequencies. Half- (f s/2) and quarter-rate (fs/4) LMS calibration for oversampled A/D decimators are proposed to reduce the computational complexity. Noble identities and polyphase decimation are used to implement these schemes to match digital noise-cancellation filters (NCF) to the corresponding transfer functions of an analog fourth-order cascade sigma-delta (SigmaDelta) ADC. Energy savings up to 30% compared to conventional full-rate (f s) schemes are confirmed using an Altera Stratix II field-programmable gate array (FPGA). The analog front-end comprises a switched-capacitor 2-2 cascade SigmaDelta ADC implemented in 0.13mum CMOS. Using differential-pair opamps with gains of only 22 db and an oversampling ratio OSR = 8, the SigmaDelta ADC system achieves 11-bit accuracy over a 9.4 MHz bandwidth with SNR = 67 dB and SFDR = 75 dB.