CMOS transceiver design for short range wireless telemetry

As feature size in silicon processes become small enough to ensure CMOS circuit design for frequencies at or above 1 GHz there will be a device to design RF circuits entirely in CMOS to reduce production costs. The recent introduction of copper interconnects into silicon processes gives RF designers a vital process alternative for wireless communication system designs. A wireless system that is particularly amenable to CMOS integration is a wireless telemetry transceiver system (WTTS) whose signals are at the ISM frequency band, 902 MHz to 928 MHz. This dissertation explores architecture and design techniques for CMOS wireless transceiver using the WTTS as a vehicle. The WTTS communicates with the central base station located in the middle of the cell geometry. The WTTS also treats the sensor information and sends it via the transmit path. The WTTS is composed of a receiver path and a transmitter path. In this thesis we evaluate the design of short range CMOS transceiver design at a number of levels. We just consider the impact of modulation schemes. Our analysis suggests that amplitude shift-keying and frequency shift-keying are the most promissary schemes as a compromise between simplicity of implementation versus performance. To provide realistic comparisons we design, build, and test both an ASK and a FSK based system. Next, we evaluate the impact of use of copper interconnect on CMOS wireless design. We introduce a high performance BFSK modulator for low power application without the use of a varactor diode. The CMOS integrated FSK detector is based on a phase locked-loop (PLL) to obtain the highest performance. The measured sensitivity approaches −96 dBm at 200 kb/sec data rates and the total receiver path power consumption is about 12.5 mW in 0.18 um copper CMOS process. The transmitter power consumption is about 3 mW at a 0 dBm output level.