| The continuing reduction in production cost and the fast improvement within the personal communication systems make it possible to extend the market and reach most people. The CMOS technology has played an important role in providing high functionality and complexity at low costs. For cheap wireless terminals, it is attractive to integrate the RF front end with the back-end signal processing to reduce assembly cost. Until now, power amplifiers for wireless applications have been produced almost exclusively in GaAS technologies, with few exceptions in LDMOS, Si BJT, and SiGe HBT. For an RF power Amplifier, the problem of using CMOS technology is more severe than other blocks in the transceiver due to the limited voltage-handling capability. The reason that the integration has not been achieved is due to the lack of RF CMOS acceptable performance. The linearity and power efficiency are lower than other technologies.; This work targets power amplifiers for short-range wireless applications. A broadband radio-frequency power amplifier is realized in a standard 0.35μm triple-metal CMOS Process. The amplifier is capable of delivering a maximum output power of 16.6dBm at 1.91GHz, and of 16dBm at 2GHz using a 3.3V supply with an overall measured power added efficiency (PAE) of 33%. The power amplifier employs a class AB output stage, which represents a compromise between efficiency and linearity. The level of output power can be controlled in 2dB steps using a number of parallel semi-cascode stages.; A power amplifier for class 1 Bluetooth standards has been implemented in 0.18μm CMOS process. The amplifier is capable of delivering 22.5dBm of maximum output power to a 50-Ohm load. This amplifier operates at class AB mode, thus it can be easily linearized to satisfy more standards in the 2.4GHz–2.5GHz ISM band. The amplifier requires a minimum number of external components, and occupies an area of 0.65mm x 0.65mm, which is the least reported area in CMOS power amplifier design. It is also the highest reported operating frequency using CMOS technology.; A class E CMOS power amplifier has been designed and tested in 0.35μm CMOS technology. The single-ended input, single-ended output amplifier delivers a maximum output power of 24dBm to a 50-Ohm load. It has 48% power added efficiency at maximum output power, while utilizing a 2V power supply.; The measurement results obtained from the fabricated power amplifiers, either in 0.35μm or 0.18μm CMOS technologies present a step forward toward showing that CMOS power amplifiers with good efficiency, and linearity are realistic despite steadily declining field-effect transistor breakdown voltages. |