| Powerline communications is a networking system with great market potential. This thesis develops some of the requirements for the analog front-end of such a system, and describes the design and testing of a receive-side analog chip. This chip consists of a 3rd-order bandpass LC filter, a low-noise low-distortion switchable-gain amplifier, and a low-distortion programmable-gain amplifier. It is implemented in a 0.18μm CMOS process, and packaged in a 44-pin CQFP. Test results show the difficulty of building very-high-linearity circuits by cancelling second-order transistor non-idealities. |
