| The purpose of this thesis is to develop accurate delay models that are amenable to optimization and to develop efficient yet accurate synthesis and optimization strategies at logic, circuit, and physical levels of design process. The thesis consists of three parts that are described below.; A large number of the optimizations in design automation can be modeled as nonlinear optimization problems, which can be solved more easily if the objective and constraints are convex. For delay optimization, this is becoming increasingly problematic since the existing models that possess such properties have become highly inaccurate in deep submicron technologies. Therefore, the first part of this thesis involves development of accurate and convex models for gate delay. The efficacy of the model is shown by its incorporation into various optimizers and performing area-delay and dynamic power-delay trade-off optimizations.; In recent technology generations, gate leakage has become a significant contributor to the total power. The reason for this is that the subthreshold leakage current of a transistor has an exponential dependence on its threshold voltage, which no longer scales in proportion to the supply voltage. Hence, the second part of this thesis targets leakage-delay optimization in contrast to the dynamic power-delay optimization formulation used in the first problem. A novel enumerative approach is proposed for threshold voltage assignment to minimize power under delay constraints. This method is then used in an approach for simultaneous transistor sizing and threshold voltage assignment to achieve a low leakage circuit configuration under given area and delay constraints.; The third part of this thesis develops a methodology to obtain delay-optimized, yet highly regular, circuits. Datapaths typically possess high regularity, and it is beneficial to preserve this regularity during synthesis so that layout tools can generate regular, and hence predictable layouts. The rigid preservation of regularity is likely to result in circuits with high delay values. The approach proposed involves controlled destruction of regularity during the synthesis process. |
