Best Delay Polarity Searching For Ternary Fprm Logic Circuit

With the rapid development of semiconductor manufacturing process,the comprehensive performance index of VLSI is becoming one of the most important indicator in the development of information industry.Due to the rapid integration of the unit area of chip,the delay and power consumption of integrated circuit is increased dramatically,which hinders the development of functional circuit diversity.The traditional digital circuit is represented as two valued logic function,however,the single line carrying capacity of the circuit is low,and the data transmission line of the system is more than that of the high speed digital signal processing.Compared with the two value signals,digital circuits based on multi-valued logic can effectively reduce the area and cost of the chip,and improve the overall communication speed of the system.In the multi-valued logic circuit,the base of the three valued signal is the smallest,and the corresponding digital circuit is easy to implement and operate,so the research of the three valued logic circuit is representative.The function expression of the three valued logic circuit can be expressed as the traditional Boolean logic,and it can be expressed as Reed-Muller(RM)logic.Generally,there are two three-valued logic function expression: Mixed-polarity Reed-Muller,Fixed-polarity Reed-Muller.N input variables three FPRM circuits corresponding to 3n different polarity logic function,the degree of expansion is different,so the best polarity searching circuit becomes the key delay optimization.In this paper,based on the establishment of the three value FPRM circuit delay estimation model,combined with the three value list polarity conversion technology and intelligent optimization algorithm,the following four aspects of the content of the study:1.The search of the best delay polarity of ternary FPRM circuit based on XOR/AND logic:according to the three values FPRM circuit function expressions and class Huffman algorithm to assess a polar FPRM delay circuit,and combined with three-valued list polar conversion algorithm to achieve the delay for small and medium-scale three-valued best-pole circuit FPRM searches.2.Delay optimization for ternary FPRM circuit based on SMPSO algorithm: research on PSO and improved adaptive mutation particle swarm optimization,combined with the three-valued FPRM circuit delay estimation model,a fitness function to evaluate the delay circuit,in order to achieve large-scale three-valued FPRM best delay circuit polarity search.3.The search of the best polarity of ternary FPRM circuit based on bat-inspired algorithm:research on the bat algorithm,combined with the three value FPRM circuit delay model,the establishment of the fitness function to evaluate the circuit delay,proposed a three value FPRM circuit delay optimization and improvement strategy.4.The optimization of delay and area of ternary FPRM circuit based on IWBA algorithm:research on the bat algorithm,the local search ability of the algorithm is improved by introducing the weed operator,and the intelligent search algorithm is used to optimize the time delay and area polarity search of three valued FPRM circuits.The proposed algorithm uses the C programming language test in the Dev-C++ integrated development environment in this paper,and the experiments were performed using the MCNC Benchmark benchmark circuits,the proposed algorithm has a significant effect on the value of ternary FPRM delay and area optimization.