Nanoelectronic circuit design and test

Controlling power consumption in CMOS integrated circuits (ICs) during normal mode of operation is becoming one of the limiting factors to further scaling. In addition, it is a well known fact that during testing of a complex IC, power consumption can far exceed the values reached during its normal operation. High power consumption, combined with limited cooling support, leads to overheating of ICs. This can cause permanent damage to the chip or can invalidate test results due to the fact that extreme temperature variations lead to changes in path delays. Therefore, even good chips can fail the test. For these reasons, thermal problems during test need to be identified to prevent the loss of yield in CMOS ICs.;In this thesis, we propose a methodology for thermally characterizing circuits under test. Using this methodology, it is possible to simulate the thermal profiles of the chips during test and prevent possible yield loss because of thermal problems.;In addition to the problems associated with power and temperature, a more important barrier is the scaling limitations of the CMOS technology. It has been predicted that in next decade, it will not be possible to scale it further. In the near future, rather than a transition to a completely new technology, extensions to CMOS seem to be more realistic.;Double-gate CMOS technology is one of the most promising alternatives that offers a simple extension to CMOS. The transistors of this technology are formed by adding a second gate across the conventional CMOS transistor gate. Designing circuits using this technology has attracted a lot of attention. However, as circuit design methods mature, there is a need to identify how these circuits can be tested. From a circuit testing viewpoint, it is unclear if CMOS fault models are comprehensive enough to model all defects in double-gate CMOS circuits. Therefore, fault models of this technology need to be defined to enable manufacturing-time testing.;In this thesis, we address the above problem using device simulations and demonstrate that while fault models defined for CMOS show significant overlaps with those for double-gate CMOS, they are insufficient to encompass all regimes of operation. This implies that new fault models are needed to adequately capture the behavior of logic gates based on this new technology.;Looking further into the future, simple extensions to CMOS will also reach scaling limitations and completely new technologies will be required to decrease the minimum feature size even further. Among many proposals, one-dimensional (1D) structures, especially nanowires, have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. It is expected that, initially, these technologies will coexist with CMOS. Therefore, researchers have been working on new architectures that integrate nanowires into CMOS. However, as the feature sizes get smaller, the fabrication process becomes defect-prone. Moreover, because of extreme device densities, it may not be possible to locate all defects. Hence, shipped chips may still be defective. Moreover, the devices in the nanometer range may be susceptible to transient faults which cause these circuits produce incorrect output values for a small period of time.;Despite the above drawbacks, it is possible to make nanoscale architectures practical and realistic by introducing defect and fault tolerance. In this thesis, we propose and evaluate a hybrid nanowire-CMOS architecture that addresses all three problems---namely high defect rates, unlocated defects and transient faults---at the same time. This goal is achieved by using multiple levels of redundancy and majority voters. A key aspect of the architecture is that it contains a judicious balance of both nanoscale and traditional CMOS components.;As the fabrication technology of nanowires evolves, it will be possible to build stand-alone nanowire-based circuits. Several small-sized stand-alone nanowire circuits have been experimentally evaluated in research laboratories. In order to speed up development of nanowire circuits, and to increase the exposure to this technology, development of physical and logic-level design methodologies and tools for implementing VLSI designs are essential. In this thesis, we discuss an automated logic-to-layout design automation tool to fulfill this need for nanowires. The tool accepts a logic-level netlist and performs logic synthesis targeting nanowire cells. Then, since the defect levels in nanotechnologies are expected to be relatively high, it performs defect-aware placement and global routing. This is followed by the following steps: detailed routing, layout display, circuit extraction and SPICE simulation. We demonstrate preliminary results for area, delay and power for various benchmarks.