Failure analysis and generation of worst-case test vectors for CMOS circuits exposed to nuclear ionizing radiation

This dissertation represents the first comprehensive academic effort in total-dose testing. A conceptual analysis was done to examine the use of process defect testing in the detection of total-dose induced failures. It was found that this approach may lead to wrong assessment of total-dose failure levels. A new theory for efficient total-dose testing of CMOS circuits was developed through the integration of the fundamental concepts of testing and the special aspects of the nature of total-dose induced failures. In order to make the problem tractable, the theory focused on static logic failure induced in CMOS combinational circuits. To determine the minimum total-dose failure level of the circuit under test, the theory shows that it suffices to test only the most sensitive node by the worst-case irradiation test vector and the worst-case post-irradiation test vector.; A new gate-level fault model, rad-weak-1, was developed to abstract static logic failure induced by total dose. The rad-weak-1 fault model is a mix of the transistor-level stuck-on and the gate-level weak-1 fault models. Moreover, the excitation of the rad-weak-1 fault model requires appropriate application of the irradiation and post-irradiation test vectors. On the contrary, the previous simple stuck-0 is just a gate-level fault model which is excited only by the post-irradiation test vector which can lead to misleading test vectors and wrong assessment of failure levels. Also, the gate-level factors that contribute to the excitation level of the rad-weak-1 faults were identified; these factors constitute the basis for determining the most sensitive node.; The first practical methodology to determine the worst-case irradiation and post-irradiation test vectors was developed. Perfect agreement was obtained between this methodology and the results obtained from the enumeration of all possible combinations of irradiation and post-irradiation inputs using circuit simulation of CMOS circuit examples fabricated using modern technologies.