A 1.5 V, 2.4 GHz Monolithic CMOS Sub-Integer-N Frequency Synthesizer for WLAN Application

Wireless local area networks (WLANs) are being extensively deployed since their introduction in the late 1990s. Low cost, high performance frequency synthesizers are indispensable in WLAN telecommunication systems. Meanwhile, integer-N phase-locked loop (PLL) architecture is commonly chosen due to its low circuit complexity and clean output spectrum with few spurs. However, designers have to face the tradeoffs between frequency resolution, phase noise performance and switching time. To solve the above dilemma, fractional-N PLL architecture is proposed, but fractional spurs emerge in the output spectrum, degrading the spectrum purity. Sub-integer-N PLL is thus a compromise between the integer-N and fractional-N PLL. Its structure is same as that of the integer-N while fractional division is achieved by a fractional frequency divider that is not relied on time-varying modulus control as in the fractional-N PLL.;This thesis presents the design of a 2.4 GHz sub-integer-N PLL for IEEE 802.llb/g WLAN applications. The proposed PLL not only acquires the advantages of the integer-N PLL, such as simple structure and good spurious performance, but also offers some benefits (for example, faster settling time and better phase noise performance) as in the fractional-N PLL design. In this design, a novel quadrature-input programmable fractional frequency divider provides fractional division ratio in steps of 0.5 by the phase-switching technique. Its key building block is a dual divide-by-4 injection-locked frequency divider (ILFD), which is realized by coupling two conventional divide-by-4 ILFDs. Two different coupling schemes are introduced, namely the cross-coupling type and coherent-coupling type. In both schemes, symmetric configuration is maintained and hence does not degrade the PLL output phase quadrature accuracy. Furthermore, the generated phase pattern for phase switching is uniquely defined, which simplifies the phase-switching circuitry and suppresses the possibility of incorrect frequency division due to glitches.;To demonstrate the feasibility of the two proposed coupling methodologies, two subinteger-N PLLs with different fractional frequency dividers have been fabricated in a 0.35 11m standard CMOS process. In design 1, the dual divide-by-4 ILFD in the fractional frequency divider is implemented with the cross-coupling scheme while the coherent-coupling scheme is used in design 2. The measured spurious tones of both designs are under -64 dBc and their measured phase noise at 1 MHz frequency offset is less than -115 dBc/Hz. The two proposed frequency synthesizers settle at approximately 32 us and their phase mismatches of the quadrature outputs are better than 38 dB (characterized by image rejection ratio). Moreover, both designs individually occupy a chip area as small as 0.70 mm2. At a supply of 1.5 V, the total power consumption for each design is below 24.1 mW.