| Rapid advancements in Internet technology are increasing the performance demand on network processors. To achieve high performance, future network processors will need to integrate multiple processors, a significant amount of Dynamic Random Access Memory (DRAM) memory, some special-purpose controllers, and the interconnection between the components, all on a single chip. The high integration of such a System-on-Chip (SoC) network processor is increasingly feasible as a result of advancements in micro-electronics technology. This thesis investigates the performance of single-chip network processor architecture by simulation of various architectural configurations. In order to provide a workload for simulation, an existing radix-tree table-lookup benchmark application for routing is adapted to generate multiple threads on demand and to support Direct Memory Access (DMA) operations. A baseline configuration is simulated first and its parameters are varied one by one to evaluate their respective effects. In order to achieve high performance most efficiently, the studied architecture needs 4 on-chip processors. Each processor needs one level of cache with a line buffer rather than two levels of caches. The on-chip bus needs a clock rate of 250 MHz or higher, which is 25% of the assumed 1-GHz processor clock rate. This bus must allow more than one request outstanding, and supporting two outstanding requests is found to be sufficient. The respective effects of varying parameters on performance are found to be a result of the trade-off between memory latency time, which results from processor stalls due to untolerated latencies in a contentionless memory system, and memory bandwidth time, which results from processor stalls due to both contention in the memory system and to insufficient bandwidth between levels of the hierarchy. |
