A mixed-signal feed-forward neural network architecture with on-chip learning in CMOS 0.18 microns

One of the main characteristics of the neural networks is their high number of interconnections between the neurons through synaptic multipliers. Interconnections occupy large area and increase the circuit complexity which limits the size of the fully parallel network. To implement large size networks, time-multiplexing should be used.; Two new mixed-signal time-multiplexed architectures are proposed for on-chip mixed-signal neural networks. MRIII is used for training the network which is more robust to mixed-signal designs. The problem of node addressing and routing is solved by performing the operations in current mode. The architectures are simple and compact and learning is performed on-chip without the host computer, which reduces the cost of learning for the network.; Mixed-signal MDACs are used for synaptic multiplication. A new compact architecture is proposed for the MDAC to reduce the area, power consumption and noise. The proposed MDAC performs the digital to analog conversion in series. Comparison shows that the new MDAC is more linear and has less noise than the conventional MDAC. The layout of the proposed MDAC is relatively easy, since it has a repetitive structure. For the first time, a new 12-bit MDAC is implemented, which enables us to perform on-chip training. The proposed 12-bit MDAC still occupies less area compared to the 7-bit conventional MDAC.; A new low-voltage class-AB high-drive buffer for driving the voltages off-chip is developed. The proposed buffer is able to drive capacitive loads up to 2nF. It also drives resistive loads down to 2kΩ from rail to rail. For compensation, a 0.2pF capacitor is used.