The Research On Test And Fault Diagnosis Methods In Analogue And Mixed-signal Circuits

As modern electronic technology develops very rapidly,the research on the fault diagnosis theories methods for analog and mixed-signal circuits are becoming very popular and also challenging. However, traditional testing methods and fault diagnosis theories can not meet the actual requirement duo to the difficulties inherent in analog and mixed-signal circuits. On the other hand, some computation intelligence technologies and modern test technologies have come forth in recent years. Considering these new technologies might provide potential solution for fault diagnosis of analog and mixed-signal circuits, research on the application of modern test is done in this dissertation. The main works are as follows:(1)The research on the current testing for mixed-signal circuit has done. The quiescent power supply current (IDDQ) testing has been accepted by the industrial community as an important test method utilized abroad in digital CMOS IC testing, and it has ever worked out magnitude contribution for the test of digital IC. And, being regarded as an extension of the IDDQ testing, the transient current (IDDT) testing has drawn more and more attention in recent years. However, most previously work were focus on digital circuit testing, and few concerned analog and mixed-signal circuit testing. Based on the study of principle, feasibility and method of current testing, a wavelet analysis based dynamic current (Idd) testing method is proposed for mixed-signal circuit fault diagnosis. The Idd testing offers an effective solution to defect-oriented testing of mixed-signal circuit. The time-frequency resolution property of wavelet analysis helps to process the Idd signature for detecting and localizing fault. Experiments were performed on a 2-bit flash ADC circuit associated with a current sensor monitoring the supply current. The results demonstrate that the proposed methods not only have higher sensitivity than pure integral and FFT method in fault detection, but also can effectively isolate the faulty region in circuit. Furthermore, the comparison between different mother wavelets on the sensitivity of fault detection is addressed.(2)The research on the built-in self test (BIST) architecture for ADC static parameters testing. A very classical technique used to determine the static parameters of ADC offset, gain is the histogram method. The histogram method is widely used for the external testing of ADCs. However, the histogram-based BIST with complete on-chip determination of the ADC parameters is usually not considered as a viable solution because of the huge amount of required additional circuitry,especially the circuit of analog signal generator. Thus, such histogram-based BIST is presented. The scheme involves an on-chip signal generation, which provides accuracy triangle-wave as the stimulant signal of ADC testing. The BIST has the advantages of high testing speed and low area overhead for easily integrated on chip. The results of simulation show the performance of this architecture.(3)The research on genetic algorithm based fuzzy neural network for analog circuit fault diagnosis has been done. A systematic approach combining fuzzy neural network, wavelet analysis and genetic algorithm is proposed for fault diagnosis of analogue circuits. The presented fuzzy neural network is developed with the improved fuzzy weighted reasoning method. The optimal feature sets is extracted to train the network by using wavelet analysis as a preprocessor. This ensures a simple architecture for the neural network and minimizes the size of the training set required for its proper training. And the adjusting of connection weights and optimization of membership functions are performed with genetic algorithms. The reliability and comparison of this method with other methods are shown by active filter examples, and the results of experimental tests show that this method can satisfactorily detect and identify the faults.(4)The research on jitter measurement of phase-locked loops (PLLs) has been done. PLLs are ubiquitous circuit blocks in RF and mixed-signal integrated circuits. PLLs are extensively utilized as on-chip clock generators to synthesize a higher internal frequency from the external lower frequency. In all of the above applications, the jitter of PLLs is one of the most critical performance parameters and a fundamental limitation in these systems. Thus, an improved method is proposed to measure the jitter on PLLs output clock accurately. In this method, the jitter is measured by an analytic signal which is extended from the real signal of PLL output clock, and a double window functions method is used in the frequency analysis to optimize the performance. The results of simulations validate the satisfactory performance of proposed PLL jitter measurement, and the better performance compared with the other methods.