| Taking advantage of continuous advances in the integrated CMOS technology, systems-on-chip (SoC) designs that include analog mixed-signal (AMS) circuits are widely used. Their applications in communications, signal processing, and embedded systems are also increasing. Even though the technology and circuit performance are improved, the analog circuits still suffer from process variations. Furthermore, testing the integrated circuits is becoming increasingly complicated and costly. Therefore, low-cost performance-tuning is required after fabrication to increase yield and to maintain high performance.;In the past, the analog and mixed-signal circuits were tested in different ways to achieve satisfactory test performance. Most common solutions used to be incorporated with automated test equipment (ATE) and device interface boards (DIB). However, for high-performance testing, the cost and time to design the AMS ATE and DIB are increasing. Alternatively, digitally-assisted on-chip built-in calibration of analog integrated circuits is an effective solution to reduce test time and cost, to improve test accuracy, and to eliminate the necessity of external test equipment. As a new approach, an off-line self-calibration technique for analog filter's cut-off frequency is proposed in this thesis. This can be done by comparing signal amplitude in the pass-band and at the cut-off frequency of the filter.;As a target application of the proposed technique, an analog low-pass filter used in a modern mobile transceiver system is selected, and this consists of RF front-end and DSP block. In the application, the cut-off frequency is accurately tuned in spite of process variations using the proposed self-calibration technique. A digital controller and a magnitude calculator are used to achieve high tuning accuracy and to minimize hardware complexity and silicon area. The magnitude calculator is required to estimate the FFT outputs that are represented with complex numbers.;To verify and demonstrate the proposed tuning technique, the circuits are implemented using a standard 130nm CMOS technology. The digital blocks consume only 0.027mm2 silicon area with 26-bit of word length of a digital data path in the control flow. The area is a significantly smaller portion compared to the main DSP block of a typical transceiver and the size of the FFT engine that consumes around 1mm2 of silicon area. The tuning error after calibration is less than 0.4% from its target. |
