Early power estimation for VLSI circuits

This research addresses the problem of power estimation at the register-transfer problems of the VLSI industry in the recent years, and a high-level power estimation capability is needed to help overcome this problem. Power estimation than previously possible, thus eliminating the need for costly and time consuming redesign efforts.; This research specifically addresses the power estimation problem for datapath circuits. Power estimation for the combinational logic portion of the datapath and power estimation of the register files were addressed separately as two subproblems of the main problem.; High-level power estimation for combinational logic blocks requires high-level predictions of circuit average activity and area. This research develops predictors for activity and area for combinational circuits, thus making it possible to estimate power at RT level. These predictors work with a functional description of the design and avoid the time consuming synthesis and mapping steps, thus making them fast.; Power estimation for register files at the microarchitectural level requires predictions of activity and capacitance of power hungry nodes in the register file. Both of these predictors are developed in this research, thus making it possible to estimate power for multiported, pipelined register files at the microarchitectural level.