| Monolithic CMOS photoreceivers in short-distance, multi-channel optical links provide a cost-effective solution to achieve multi-gigabit link capacity. To investigate such links, various integrated photoreceivers were designed, implemented and tested in CMOS 0.18μm. To reduce the tail-like effects due to slow carriers in the substrate, a spatially-modulated (SM) detector structure is successfully demonstrated. The geometric properties and PN-type diodes were important factors on the photoreceiver performance. The test chip operated at 1.8V with a die area of 1 x 1 mm2.; Crosstalk is another serious issue to consider in the integration of photoreceivers in CMOS technology. Four transimpedance amplifier (TiA) designs were compared in terms of their rejection to substrate noise. A substrate model was incorporated into the TiA circuits, and bulk-noise rejection trends were obtained. The four TiA designs were implemented in CMOS 0.18μm chip, and other test structures that pertained to noise generation, noise sensing, and inter-channel coupling mechanisms were also included. Analysis and experimental results showed that the TiA design with small transconductance was more susceptible to substrate noise. This test chip operated at 1.8V with a die area of 1.5 x 1.5 mm2. |
