Analysis Of Substrate Resistor' Impacton CMOS Circuit

Many parasitic effects, which can be ignored in long channel circuit, must be paid much attention in the multiple function and high density integrated circuit, due to huge die size and high speed clock signal. In real circuit design, same device performs differently when in various substrate status. That's why we need to establish an effective method to detect substrate effects. This article is to establish a simple and clear circuit model to analyze and study the substrate parasitic effect, which is caused by substrate resistor and will impact circuit performance in various aspects and to spread this method in different situations. From previous study, most researches on substrate parasites focus on the substrate directly beneath the MOSFET. Related simulation model and calculation formula are relatively mature. This article wants to add additional substrate elements mainly among MOSFET devices and to provide a substrate parasitic model abstracted from a more comprehensive physical structure. Usually substrate situation is not given special consideration when doing circuit design; neither CAD tool can extract the substrate parasitic parameter outside the MOSFET. In this case, the model and the analysis method mentioned in this article will be a good compensation. It's a good reference especially for high speed and high accuracy circuit. In the article, we make a parasitic substrate model on the existing MOS model, and use this model to do simulation for each single MOS, accumulated effect circuit and some useful analog circuit. From the simulation data, we can clearly observe the instability of substrate voltage, caused by substrate resistor, will cause some trouble in both analog and digital circuit. It will benefit the circuit designers by making more tight rules and designing insurance circuit to guarantee the circuit design.