Cmos Rfic Substrate Noise Analysis And Its Impact On The Vco Performance

In the past few years, wireless personal mobile and cellular communications have consistently been one of the hottest growth areas. The push for low cost, low power and smaller size has motivated the combining of radio frequency circuits with baseband digital circuits for wireless application. One design challenge of such RF System-on-Chip is substrate noise generated by the digital circuit on SOC can have a significant impact on sensitive RF circuits sharing the same substrate. Voltage Controlled Oscillator (VCO) is a very sensitive RF block in most RF SOC chips. Substrate noise coupled into VCO will modulate the oscillator signal in frequency and amplitude. The modulation effects generate sideband spurious around the local oscillator and degrade the phase noise performance of VCO. This paper presents a lightly-doped substrate model of SMIC 0.18um RFCMOS process. The model can be used for prediction of the impact of substrate noise on RF circuit by simulation. Substrate noise generation, isolation, and impact for an LC-VCO are investigated in this paper.