| The recent growth in microprocessor performance has been a direct result of designers exploiting decreasing device feature sizes, while at the same time deepening the depth of pipelines. As transistor sizes continue to shrink, the traditional gains associated with smaller feature sizes will be degraded due to the adverse effects of wire scaling. The consequences of technology scaling on circuit performance have recently become a topic of significant importance, especially in arithmetic circuitry such as digital multipliers, which exhibit highly irregular interconnections.;A digital multiplier architecture will be introduced that alleviates some of the problems associated with interconnect scaling, in addition to allowing for simple variable precision reconfiguration. Regulated by a 2-bit control signal, the multiplier is capable of true double and single precision multiplication, as well as fault tolerant and dual throughput single precision execution. The architecture proposed in this paper is centred on a recursive multiplication algorithm by Danysh and Swartzlander, where a large multiplication is carried out using recursions of simpler base multiplier modules. This multiplication algorithm presents greater regularity in design than standard column compression multipliers, while avoiding the linear latency of array multipliers.;A separate investigation of the recursive multiplication scheme has lead to favourable results for a design methodology recommended for future arithmetic architectures, which makes use of the proposed "locally optimized array" paradigm. Furthermore, a study of column compression techniques will be presented; this includes a novel suggestion for an optimized 4:2 compressor distribution in partial product reduction trees, and an overview of the transistor level configuration of arithmetic cells. |
