Evaluation of new multiply and multiply-accumulate structures in FPGAs

Today's multimedia applications and embedded hardware for everyday tasks utilize more and more reprogrammable logic by using FPGAs. The use of FPGA technologies allows for later updates of processing algorithms and the ability to add new features. Most multimedia application algorithms require the use of multiplication, multiply-add, or multiply-accumulate structures to perform the calculation, translation, and filtering for the application.;A. D. Booth developed a method for performing binary multiplication that could be done using simple hardware methods. This method was later improved upon by further reducing the number of partial product rows required for performing the multiplication operation. This modified Booth architecture allowed for fast multiplication in silicon devices.;These methods over the years have been improved upon looking to increase the speed or versatility of its applications. J. Y. Kang and J. L. Gaudiot developed a fast 2's complementing operation in the modified Booth encoder of the final partial product stage to improve multiplier performance in CMOS. F. Elguibaly developed a modified pipeline by pre-calculating part of the result in a modified Booth multiply-accumulate design to improve speed in CMOS technology.;These two concepts are evaluated in two different FPGAs using VHDL against standard modified Booth designs for multipliers, multiply-adders, and multiply-accumulators. In each type of arithmetic architecture, multiplication operations of 8x8, 9x9, 16x16, and 18x18 are evaluated. For the multiply-add and multiply-accumulate operations, multiply-adder and accumulate widths of 2n+1 and 48, where n is the operand bitwidth, are examined. These are contrasted with the FPGAs embedded multiplier structures' performance, and the performance of using "*" and "+" operators in VHDL allowing the tools to generate their own structures in logic.;The evaluation was to determine if these specific improvements offered overall improvement over standard modified Booth techniques in FPGA technology, and that this improvement was available in portable code that was consistent over various FPGA families. The FPGAs targeted are an Altera Cyclone- III FPGA device and a Xilinx Spartan3A-DSP FPGA device. Architectures are compared on speed and area using synthesis results in their respective FPGA development tool suites.;The research shows that Kang and Gaudiot's multiplier design performs best in most cases in Altera FPGA hardware, but only performs best in two bitwidths, 9x9 and 18x18, in the Xilinx hardware. The Elguibaly design does not perform well in most cases. All new modified Booth designs performed better in speed than the "*" based designs.The research shows that there is not one specific design that is consistently the best across multiple FPGA platforms, but that the concepts presented in Kang and Gaudiot's work do provide improvement upon standard modified Booth techniques in a lot of cases. The rewards due to the modifications of the multiply-accumulate pipeline from Elguibaly's work do not translate over into FPGA based designs.