Design and analysis of low-power and noise-tolerant multiply accumulate units

The multiply accumulate unit represents an essential building block that is used frequently to build high performance signal processing systems. With the increasing demand on battery powered portable applications, power consumption is being viewed as a major design issue. It motivated the need to develop new low-power design techniques to implement the basic cells and building blocks that are frequently used to construct large systems. Another issue that emerged with the deep sub-micron technology is noise sensitivity. The reduced dimensions of the devices and the lesser spacing between interconnects are making the circuits more susceptible to noise, The most challenging part is to maintain high performance in terms of operating speed and occupied silicon area while attempting to reduce the consumed power and making sure that the circuit is functioning properly under the influence of surrounding noise sources. This thesis investigates low power and noise tolerant design of circuits and architectures used to build the multiply accumulate unit at different levels On the architecture level, a decomposition approach for low-power design of pipelined multipliers is developed. Power consumption optimization is achieved at the architecture level by eliminating the unnecessary switching activity using clock gating techniques and preprocessing operations on the input pattern. A new data merging architecture for high-speed multiply accumulate units is proposed. Increasing the speed of operation is achieved by using the bits of the accumulated operand to fill the free input lines of the compressor circuits. The need for a separate accumulator is eliminated which results in significant performance improvements. For noise sensitive applications, an inductive noise reduction technique is developed for pre-charging dynamic circuits. The technique is based on avoiding simultaneous pre-charging of the dynamic cells available in the array and hence, reduces the magnitude of the current pulses delivered from the supply.; On the circuit level, several structures and circuit design techniques are proposed to implement the 1-bit full-adder cell. The proposed designs have the advantage of low power consumption and high operating speed. Moreover, they occupy small silicon area due to the small transistor count.; Cadence tools are used for design verification. Complete layouts are also generated and extracted, to include the effect of interconnects and parasitic components, and simulated using Hspice. The technology used for prototyping is the 0.18-micron double metal CMOS technology.