| The design of a SoC platform for network protocols conversion resulted in proposing specialized architectures. It is possible to optimize these systems by separating the processors, the memories, and the inputs/outputs (I/Os). These optimizations also eliminate bottlenecks due to memory throughput and I/O integration.;An architecture that clusters distributed units around a main memory was conceived. It was validated on an Integrator/AP evaluation platform from the ARM corporation. This architecture enables analyzing the process of converting IEEE 802.3 protocol (Gigabit Ethernet, 1 Gbps) to IEEE 1394 (Firewire, B, 800Mbps), and vice versa.;Based on the study of these protocols and the various families of existing network processor architectures, we aim at developing a new, more effective and efficient architecture. The design of such architecture requires using a high level design methodology. This approach leads to behavioral and architectural modeling of the targeted system.;In order to optimize this architecture, we carried out simulations on a behavioral model by using a set of tests vectors that represent the worst case of a packet stream to be converted. These simulations showed that the proposed architecture, after the introduction of significant modifications, reached a conversion rate of 100% of the input stream, while the application of these same tests vectors on the initial architecture validated on the Integrator/AP platform gave a conversion rate of 50%. We show how high level modeling enables tuning an efficient software/hardware architecture. (Abstract shortened by UMI.). |
