| The main objective of this thesis is to establish methodologies for the optimal design of the multilevel interconnect network in a GSI chip. A stochastic wiring distribution is used to develop an optimal n-tier reverse-scaling methodology for the design of each metal layer. An optimal repeater insertion methodology is developed that minimizes the number of metal layers, clock period, area or power dissipation. In order to design the multilevel interconnect network for future high speed GSI microprocessors, analytical models are developed for the transient response of distributed rlc interconnects. These models are used to develop compact models for time delay, crosstalk and repeater insertion in distributed rc and rlc interconnects. The new models are used to investigate the impact of inductance on a multilevel interconnect architecture and to optimize the aspect ratios of the physical dimensions of different metal levels. The models and methodologies have been incorporated into a software tool called MINDS, which stands for Multilevel Interconnect Network Design Simulator. |
