Gigabit/second clock and data recovery circuits for local area networks

The demand for high data rate information at the subscriber terminal has increased the need for inexpensive high-speed serial data receivers. The most challenging part in the receiver is the design of the clock and data recovery (CDR), which defines the performance of the overall transceiver system. This thesis deals with the integration of high speed PLL-based CDR circuits for serial receiver applications.; This thesis proposes and implements a design methodology for an economical, fully integrated and high speed PLL-based CDR with a bang-bang phase detector in a CMOS process without the use of integrated inductors and off-chip capacitors. To overcome the problems associated with the use of an on-chip loop filter capacitor, a novel four-step bang-bang phase detector is proposed and used in the CDR design to meet the requirements of a short serial link in local area networks (LAN) applications.; A 5Gb/s CDR implemented in a 0.18mum CMOS process with a supply voltage of 1.8V was designed and characterized. Extensive isolation and decoupling techniques in the layout of the CDR are used to reduce the effect of cross-talk and the power supply and ground noise. The CDR area was 0.3mm2 and the total power dissipation was 80mW. The total generated jitter was 4.8ps (rms). The CDR achieved a bit error rate of 10-12 with a data eye opening of 35%.; A 10Gb/s CDR was also implemented in a 0.13mum CMOS process. The challenge of designing the CDR in such a process is to overcome the limitations imposed by the 1.2V power supply voltage. A 10Gb/s random pattern generator with a random sequence of 211-1 was implemented on the same chip to eliminate testing problems associated with transferring off-chip high speed test patterns to the CDR. The CDR area was 0.6mm2 and the total power dissipation was 140mW The maximum generated jitter was 3ps (rms). A data eye opening of 50% was necessary for the CDR to achieve the 10 -12 bit error rate.