| Delta-sigma analog-to-digital converters (ADCs) are widely used in audio applications, but their use in video applications is emerging. By introducing novel decimator and modulator design flows, this thesis advances the state-of-the-art in delta-sigma data conversion and image sensing. As the approach concerns arrays of many ADCs, it is essential to minimize the layout area and power consumption of each ADC. For maximum scalability, each column or pixel must include a decimator. Conventional decimation, e.g., based on comb filters, is unsuitable for this purpose. Instead, finite-impulse response decimation may be realized efficiently in bit-serial fashion by generating optimal coefficients at the chip-level. As for the modulator, architectural choices and modeling approaches are taken to reduce both area and power while realizing specifications and tolerating mismatch. Very small capacitors suffice to achieve reasonable specifications. These design flows are used with 0.18µm CMOS technology to fabricate specific designs. In a first chip with several data converters, column and pixel-level ADCs achieve figures of merit (150 and 137dB) comparable to state-of-the-art delta-sigma ADCs, but with smaller modulator areas (1,850 and 627µm2). In a second chip with two image sensors, logarithmic pixels are combined with column and pixel-level ADCs to make digital video cameras. Both image sensors achieve peak signal-to-noise-and-distortion ratios (35 and 46dB) comparable to the human eye and better than state-of-the-art logarithmic cameras. Although the present results are immediately useful, the approach is also suitable for low-voltage nanoscale CMOS processes, which would further reduce the layout area and power consumption. |
