Fabrication Technology and Device Simulation of Enhancement-mode AlGaN/GaN Transistors

GaN based high electron mobility transistors (HEMTs) technology has witnessed rapiddevelopment during the last decade in the applications of high-frequency power amplifiers,high-efficiency power switches and high temperature integrated circuits (ICs). ConventionalAlGaN/GaN HEMTs are fabricated on the Ga-face C-plane epitaxial wafers with inherentstrong spontaneous and piezoelectric polarization that yields high two-dimensional electrongas (2DEG) density. While the high 2DEG density consequently results in high currentdensity, the channel is normally-on and requires a negative gate bias for pinch-off, presentingthe device as depletion-mode (D-mode). However, in circuit applications, the enhancement-mode(E-mode) devices with positive threshold voltage are highly desirable for the reducedcircuit complexity and fail-safe operation. By replacing the D-mode devices with E-mode ones, the negative-polarity supply voltage can be eliminated from the power amplifier andpower switch modules. The monolithic integration of E/D-mode HEMTs also allows theimplementation of the direct-coupled FET logic (DCFL) integrated circuits that becomes thetechnology of choice for GaN digital ICs due to the lack of high-performance GaN p-channeldevices. In general, E-mode operation of the GaN devices would deliver enhancedperformance in circuit and system levels in RF, power, and mixed-signal applications. The first part of this thesis presents a fabrication technology of E-mode AlGaN/GaNHEMTs using standard fluorine ion implantation equipment that is widely available insemiconductor micro-chip fabs. An 80 nm silicon nitride layer was deposited on the AlGaNas an energy-absorbing layer that slows down the high energy (~25 keV) fluorine ions so thatmajority of the fluorine ions are incorporated in the AlGaN barrier. The threshold voltage wassuccessfully shifted from -1.9 V to +1.8 V, converting depletion mode HEMTs toenhancement-mode ones. The fluorine ion distribution profile was confirmed by SecondaryIon Mass Spectrometry (SIMS). The slowdown threshold voltage shift at positive region isrevealed by the plasma ion implantation experiment and is explained by the location-dependentmodel. An insulator between gate and AlGaN can be used to increase theefficiency of threshold voltage shift modulated by fluorine ions. The second part of this thesis focuses on investigating the underlying device physics(especially the drain induced barrier lowering (DIBL) effect) in a new metal-2DEG tunneljunction FETs (TJFETs) by numerical simulation. It is found that although the 2DEG channel of TJFETs is "ON" at OFF-state, the drain influence on the source Schottky tunnelingjunction is blocked well at high drain bias due to the pinch-off at the drain-side gate edge of aTJFET with relatively long channel. The short channel TJFETs show a weaker dependence ofDIBL effect on the buffer compensation doping than the conventional metal-insulator-semiconductorhigh electron mobility transistors (MISHEMTs), because the DIBL effect inTJFETs is mainly suppressed by the source Schottky junction. Even with zero compensationdoping, short channel TJFETs exhibit relatively small DIBL effect (e.g. 166mV/V for Lg =100 nm). The gate capacitance partitioning in the AlGaN/GaN TJFETs is investigated by bothnumerical simulation and experimental characterizations. Representative characteristics suchas the gate-bias dependent parasitic resistance and the gate induced barrier lowering effect ofthe Schottky tunnel junctions are identified. The gate capacitance partitioning behavior inTJFETs is explained by the gate induced source Schottky barrier lowering effect. The resultsfrom this work provide valuable design guidelines for performance optimization in TJFETs.