Viterbi decoders for mobile and satellite communications

The design and FPGA implementation of configurable, high performance Viterbi decoders targeted for wireless and satellite communication transceivers, are presented in this thesis. Two Viterbi decoder circuits one for constraint length equal to 7 for satellite applications and the other for constraint length 9 for wireless transceivers have been realized. The performance and circuit characteristics were confirmed through simulation and functional verification. The designs for constraint lengths of 7 and 9 operate for code rates of 1/2 and 1/3. Furthermore, the trace-back length (TBL) can be reconfigured and set at values ranging from 35 to 64 in steps of five. The modular architecture adopted permits the integration of two ACS (add-compare-select) units to satisfy the computational requirements, which are a function of the constraint length and trace back length. The designs have demonstrated the effectiveness of scaling and look-up techniques in reducing circuit requirements associated with branch metric computation and path metric determination. Functional and VHDL code simulation results have confirmed performance improvement by 0.4 dB upon changing TBL from 35 to 50 for constraint length 7. FPGA implementation results based on Altera's APEX technology, have confirmed the Viterbi decoder throughput to be 2 Mbps.