Fabrication and Characterization of III-V Tunnel Field-Effect Transistors for Low Voltage Logic Applications

With voltage scaling to reduce power consumption in scaled transistors the subthreshold swing is becoming a critical factor influencing the minimum voltage margin between the transistor on and off-states. Conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) are fundamentally limited to a 60 mV/dec swing due to the thermionic emission current transport mechanism at room temperature. Tunnel field-effect transistors (TFETs) utilize band-to-band tunneling as the current transport mechanism resulting in the potential for sub-60 mV/dec subthreshold swings and have been identified as a possible replacement to the MOSFET for low-voltage logic applications. The TFET operates as a gated p-i-n diode under reverse bias where the gate electrode is placed over the intrinsic channel allowing for modulation of the tunnel barrier thickness. When the barrier is sufficiently thin the tunneling probability increases enough to allow for significant number of electrons to tunnel from the source into the channel.;To date, experimental TFET reports using III-V semiconductors have failed to produce devices that combine a steep subthreshold swing with a large enough drive current to compete with scaled CMOS. This study developed the foundations for TFET fabrication by improving an established Esaki tunnel diode process flow and extending it to include the addition of a gate electrode to form a TFET. The gating process was developed using an In0.53Ga 0.57As TFET which demonstrated a minimum subthreshold slope of 100 mV/dec. To address the issue of TFET drive current an InAs/GaSb heterojunction TFET structure was investigated taking advantage of the smaller tunnel barrier height.