Research On ESD Characteristics Of Fully Depleted TFET Devices

Traditional Metal Oxide Semiconductor Field Effect Transistor(MOSFET)has a subthreshold swing limit of 60mV/dec at room temperature,which limits the application of MOSFET devices in ultra-low power integrated circuits.Under this background,the tunneling field Effect Transistor(TFET),which can break through the subthreshold swing limit of 60mV/dec,has been developed.Tunnel Field Effect Transistor became a very competitive candidate to replace MOSFET in a low power integrated circuit.In the production of integrated circuits,Electrostatic Discharge(ESD)is one of the main causes of integrated circuit device failure.For deep submicron small devices,ESD impact is more likely to lead to its failure.Therefore,the main contents of this paper are to explore the different characteristics of TFET under ESD impact and to improve the structure of conventional TFET devices to obtain better ESD performance.This paper first introduces the ESD discharge model and protection principle,describes the method of determining the ESD value range of the TFET device according to the design window,and introduces the process of using Sentaurus TCAD software to simulate the TFET to obtain more accurate ESD data.On this basis,the following three improved TFET-type ESD protection devices are proposed:(1)SiGe source/drain P+N+N+doped tunneling field effect transistor(SiGe S/D PNN TFET):Compared with conventional TFET devices,the triggering voltage of SiGe S/D PNN TFET is reduced by 66.3%,and the failure current is increased by 20%.The ESD performance of SiGe S/D PNN TFET can be improved by adjusting the leakage level and channel doping concentration of SiGe S/D PNN TFET,as well as the mole ratio of Ge.In addition,the unique single-current path phenomenon of the SiGe S/D PNN TFET is analyzed when the source gate is grounded and the ESD pulse current is applied at the drain stage.(2)Dual-gate fully depletion tunneling field effect transistor(DG FD TFET):Compared with conventional dual-gate TFET devices,the trigger voltage of DG FD TFET is reduced by 42.9%and the failure current is increased by 10.8%.At the same time,the influence of different parameters on the ESD window of DG FD TFET is considered.The better ESD window can be obtained by adjusting the doping concentration of DG FD TFET leakage level and channel,the depth of tunneling junction and the length of leakage stage.Silicon on insulator(3)fully depleted field effect transistor(FD SOI TFET):compared with the conventional TFET device,FD SOI TFET trigger voltage reduced 48%,the failure of current was reduced by 26.8%,adjust the FD SOI TFET leakage level and channel doping concentration and the cover layer thickness of buried oxygen,all can improve its ESD design window,get better ESD design window.The proposed SiGe S/D PNN TFET,DG FD TFET and FD SOI TFET all use the fully depleted structure,which can improve the ESD performance compared with conventional TFET devices.The single current path and improved ESD parameters found in this paper are helpful for the design of better ESD protection devices and the construction of more complete ESD protection networks based on TFET devices in the future.