Novel Vertical Tunnel Transistors for Continued Voltage Scaling

In the last few decades, MOSFET scaling has enabled smaller and faster transistors that consume less power per operation. But as device dimensions were shrunk into the sub-45nm regime, non-scalability of the subthreshold swing (SS) to below 60mV/decade has resulted in significant increase in the OFF state current (IOFF) and the stand-by power dissipation. Obtaining the required ION without an increase in IOFF is greatly needed to further scale VDD and reduce circuit delay and power consumption simultaneously. Impact ionization FET, feedback FET, nano-electro-mechanical FET, p-i-n and p-n-p-n tunnel FETs were proposed as novel device concepts that can achieve sharper SS than 60mV/decade. In this thesis, a detailed comparison of these steep subthreshold devices in terms of circuit speed and power dissipation is presented, and the challenges for each device to become a viable MOSFET alternative are outlined. P-n-p-n tunnel FET is identified as one of the more promising steep subthreshold devices in terms of circuit delay and power. Tunnel FET performance depends strongly on the dopant profile steepness at the tunneling junction. Very sharp (∼1.5nm/dec) optimized channel dopant profile for the p-n-p-n tunnel FET is demonstrated by molecular beam epitaxial (MBE) growth. Devices are fabricated with a low thermal budget vertical process flow. It is found that the p-n-p-n tunnel FET has improved subthreshold swing, ION and tunneling resistance over a p-i-n tunnel FET, potentially opening a path to reduced VDD operation.