| Advances in microelectronic technologies allow development of complex digital systems. Consequently the functional verification of such systems becomes increasingly difficult. Moreover, since manufacturing costs of such circuits increase at the same time as the complexity of a circuit, functional errors detected following its manufacture generate costs that can seriously affect its commercial profitability. It is thus necessary to perform a more accurate verification while respecting the schedule imposed by time-to-market constraints. Hence, the development of new verification methodologies is essential to deal with the current constraints governing the development of digital circuits. These new verification methodologies must be aimed at accelerating verification tasks and at enhancing the quality of the overall verification process.; This thesis brings a contribution to the functional verification process by introducing two verification methodologies. The first method proposed in this thesis is a test-bench design methodology that promotes reuse. This method is based on the use of a Hardware Verification Language (HVL), the e language, that allows using object-oriented and aspect-oriented programming techniques. Hence, an object-oriented and an aspect-oriented partitioning dedicated to test-benches design are proposed in order to increase their reuse potential. This method attempts to accelerate test-bench design and implementation. (Abstract shortened by UMI.)... |
