Equivalence verification for null convention logic and latency-insensitive circuits

NULL convention logic and latency-insensitive circuits are delay-tolerant circuits that can be synthesized from a synchronous specification. These design paradigms can use existing CAD flows to implement circuits that are robust to process variations and wire delays. Verification is an indispensable phase of any commercial design cycle, and needs to be addressed in order to exploit the potential advantages of these design paradigms. Delay-tolerant circuits are of asynchronous nature. Therefore, timing behavior of these delay-tolerant circuits are very disparate from the synchronous specifications, and verifying equivalence of the synthesized circuit to the synchronous specification is one of the main challenges. However, there is no existing work in the literature that address this challenge and still remains an open problem. This study makes an initial effort in developing equivalence verification methods and equivalence checking tools for these design paradigms.