Source/drain and gate design of advanced MOSFET devices

Further scaling of the planar MOSFETs beyond 50nm regime is becoming very difficult due to practical and fundamental limitations. Novel device structures and careful device design are needed to meet the challenges. Ultra-thin-body (UTB) Silicon-on-insulator (SOI) MOSFETs is the most mature device structure to continue the scaling of MOSFETs. Raised source/drain (S/D) is a promising structure to reduce the S/D series resistance introduced by the UTB. We developed a poly raised SID structure with air spacer. The thick S/D was self-aligned to the gate electrodes. The parasitic capacitance introduced by the raised S/D was reduced by the air spacer.; Direct tunneling through gate dielectric is one of the fundamental limitations of scaling. High-K gate dielectric with reduced equivalent-oxide-thickness (EOT) has to be used in the scaled MOSFETs. However, high-K gate dielectric introduces fringing E-field effect. The air spacer is studied and proved to be effective for suppressing the short-channel-effect (SCE) of devices with high-K gate dielectric and raised S/D. By using air spacer, the device performance was also improved because of the reduced parasitic capacitance.; The double-gate SOI (DG-SOI) MOSFETs is the most promising candidate for further scaled MOSFETs. A new high performance DG-SOI was presented. The fabricated DG-SOI demonstrated good SCE suppression and improved drive current. Besides providing a novel process to fabricate high-performance DG-SOI, the fabricated DG-SOI is also suitable for gate misalignment study.; Gate misalignment is one of the key issues introduced by DG-SOI. The S/D asymmetric effects caused by gate misalignment were carefully analyzed based on both experimental data and simulation results. Besides SCE and performance, the gate current increased quickly with the increasing gate misalignment and it is asymmetrical to source and drain. At the same gate misalignment, the inverter consisting of DG-SOI with bottom gate shifts to drain side exhibits twice the gate leakage as the inverter consisting of DG-SOI with bottom gate shifts to source side.