Power optimization in integrated circuits

With the advancement of technology, hand held devices and personal gadgets are an integral part of the human life style, with expectations of more design features, higher throughput, and longer lasting battery power. Also, the semiconductor industry's drive to adhere to Moore's Law has resulted in remarkably low-cost memory, immense computing power, and high-speed connectivity, in packages that are low cost and have reasonable power. The semiconductor industry is now delivering integrated circuits with transistors that are made using 14 nm manufacturing processes. At such advanced processes, leakage power is almost comparable to the dynamic power even at the active mode of operation of the digital integrated circuit (IC).;Both dynamic and leakage power are directly proportional to the transistor active area. Leakage power can be reduced by choosing higher threshold voltages (VT's) for the transistors. Current semiconductor processes offer at least two threshold voltage options and, in addition, it is common for standard cell libraries to augment the effective threshold voltage options by adding longer channel length versions of the cells. The longer channel lengths, on the order of 10-15% longer, reduce leakage appreciably in the same manner as a higher threshold voltage and hence are treated as another threshold voltage option.;The International Symposium of Physical Design (ISPD) contests for discrete (library-based) gate sizing without wire loads (2012) and with wire loads (2013) have led to appreciably improved algorithms. However, significant changes in cell sizes require some type of re-placement and rerouting which invalidate the wire loads upon which the sizing was performed. In turn, sizing optimization must be re-performed with these new wire loads. To the best of our knowledge, it has not been shown how much power and/or leakage reduction can be obtained for actually laid out circuits, nor whether the process even converges.;Our gate sizing and VT optimization algorithm achieves leakage reduction results comparable to the best reported to date for the smaller circuits and significantly better results for the largest circuits (e.g., close to 1 million cells) in the ISPD set. We then interfaced our tool with a leading EDA synthesis and layout tool using a TI 45nm multi-VT cell library. We developed an ECO based algorithm and script for use with the EDA placement and routing tool, such that the post layout leakage minimization converges after just one sizing/layout iteration. Compared to the leading multi-VT EDA synthesis and layout solution, we demonstrate a 15% reduction in power post layout on average for a set of large benchmark circuits, and as much as a 28% reduction in power post layout.;We also developed an internal timing engine which uses a fast and effective algorithm that accurately estimates the delay and slew rate at each wire end point based on RC extraction regardless of the number of RC sections. This wire delay calculation algorithm also accurately and efficiently computes the effective capacitance seen at the output of each gate. The delay results produced by this algorithm has an error of less than 2% compared to Primetime and 0.39% compared to Hspice. All the algorithms developed for power optimization are efficient, with an ability to handle contemporary ASIC designs with at least 1million cells.