Design Of A Low Voltage, Low Power-consumption, And Multi-trip Point Low Voltage Inhibit

The project is focused on the design and research of Microprocessor SupervisorCircuits in Multi-voltage System (alias Low Voltage Inhibit, LVI for simplify). Theperformance of LVI determines the security, reliability and stability of MCU directly.It is difficult that we should design the LVI, which should monitors five-level supplyvoltage (5V, 3.3V, 3V, 2.4V and 2V), in a wide temperature range from -40°C~140°Cand under the low power consumption below 100uA with 0.5um standard CMOSdigital process. The project has been successfully finished by circuit design,simulation, layout and verification. The main work accomplished can be summed upas follow: Based on the function and spec of LVI, the circuit is partitioned into fiveself-functional blocks: CMOS Current Reference Block (alias 'current_ref'),Bangap Voltage Reference Block (alias 'bandgap'), Threshold VoltageSelection and Comparison Block (alias 'lt'), Output Buffer Block (alias'buffer') and 5-Supply Voltage Selection Block (alias 'decoder'); Designed and simulated all the blocks of LVI using a precise Spicesimulation tool ---Mica, and adjusted structures and parameters to meet thespec; Reviewed the design with a fast Spice simulation tool ---Nanosim, in orderto find the problem about power consumption and to validate the designspec of low power consumption; Finished the whole layout of LVI using Virtuoso layout tool, and performedthe verification of DRC, ERC and LVS by Hercules and Dracula.The project is cooperated by Freescale Qiangxin(Tianjin) Co., Ltd. and TianjinUniversity ASIC Design Center. The achievement of this project would promote thedevelopment of the reliability on power supply and electric system.