| Inductive noise on microprocessor power lines, known more commonly as the dI/dt problem, can degrade the performance and reliability of a CPU. While aggressive power saving techniques such as clock gating can reduce average power consumption, they unfortunately increase the variability of current drawn by the processor. This leads to increased inductive power supply noise, which can cause circuits to fail. Although microarchitectural policies promote the problematic current variations, traditional methods of coping with inductive noise focus on electronic packaging techniques. Given recent industry trends, these increasingly expensive packaging approaches may not adequately solve the dI/dt problem in future processors.; This thesis examines the dI/dt problem at the microarchitectural level, and introduces novel techniques to characterize and reduce the effects of inductive noise. The effects that clock-gating and other power-saving techniques have on inductive noise make microarchitectural analysis a natural option.; The material presented in this thesis applies theory from other branches of electrical engineering to address two problems related to inductive noise: dI/dt workload characterization and microarchitectural voltage regulation. The frequency sensitive nature of inductive noise makes Fourier and wavelet analysis effective tools for dI/dt characterization of programs. This thesis also presents a strategy for applying feedback control to the design of microarchitectural voltage regulation mechanisms. These controllers make pipeline and instruction scheduling decisions that prevent dangerous power supply fluctuations, decreasing the burden on the electronic packaging, and ultimately helping to reduce cost and complexity of the power delivery system. |
