VLSI architecture for a dual base multiplier

Computational complexity in a digital design depends upon the number of zeros of input data in the corresponding number system. Hence, selection of a number system is very vital in realizing such design. The Number Systems used in traditional multipliers result in less sparse representation of input data, increasing the computational complexity. A new number system called Double Base Number System (DBNS) has evolved to address these limitations. This Number System has very sparse representation and uses binary digits. Its sparse representation enables less number of computations to be performed, which improves speed of arithmetic operations. This thesis presents an implementation of a multiplier that uses Double Base Number System.