Tree Search Based MIMO Detectors: Algorithms and VLSI Architectures

In the past few years, Multiple-Input Multiple-Output (MIMO) communication has been recognized as a promising technology to improve the quality of service and/or to achieve high data rate for wireless communication systems. It has also been adopted as part of a number of industry standards such as WiMAX, LTE, and the next generation WLAN (802.11n). However, the lucrative features of MIMO communications come along with the costs of significantly increased system complexity, including area, as well as power consumption. Thus, in MIMO systems, it is always a challenge for researchers and engineers to design a receiver structure that can achieve optimal quality of reception with manageable system complexity.;In this thesis, we present efficient design for the spatial multiplexing MIMO receivers at both the algorithm and VLSI architecture levels. We consider that the MIMO detector and the channel decoder are two major blocks and attempt to optimize them in a joint sense. First of all, we focus on the design of MIMO detector and propose two approaches. The first design presents a novel algorithm and architecture for K-Best detection. The algorithm examines a much smaller subset of points in the tree structure as compared to conventional K-Best detector; while still achieving near-optimal performance. The VLSI architecture of the detector is based on a pipelined sorter-free scheme such that high throughput and low complexity is achieved. The proposed K-Best detector is designed to support a 4x4 64-QAM system and can achieve an average throughput of 285.8 Mbps at 25 dB SNR with 210 Kgates area at 12.8 mW power consumption. The second design demonstrates an algorithm and VLSI architecture of combining the features of classical depth-first and breadth-first methods. Techniques to reduce complexity while providing both hard and soft output detection are also presented. This detector supports a 4x4 64-QAM system and can achieve an average throughput of 257.8 Mbps at 24 dB SNR with an area equivalent to 54.2 Kgates and a power consumption of 7.26 mW for hard output scheme. For the soft output scheme it achieves an average throughput of 83.3 Mbps across the SNR range of interest with an area equivalent to 64 Kgates and a power consumption of 11.5 mW.;Finally we present an approach to perform joint detection and decoding for MIMO systems which utilize convolutional codes. The BER performance of this approach is significantly better than that of systems which utilize separate detection and decoding blocks. In particular, for a reference 4x4, 16-QAM system using a rate 1/2 convolutional code with generator polynomial [247,371] and a constraint length of 8, improvements in SNR of 2.5dB and 3dB are achieved over conventional soft decoding at a BER of 10 -5. The proof of concept VLSI architecture is provided and a novel way to reduce memory usage is demonstrated. The proposed design can achieve an average throughput of 216.9 Mbps at a SNR of 13 dB with area equivalent to 553 Kgates.