Research On Algorithm And VLSI Implementation For Very High Throughput WLAN Receiver

Since Wireless Local Area Network(WLAN)was created in 1997,it has become one of the most popular commercial wireless communication standards and already evaluated to the 6th generation.Higher order modulation,wider bandwidth,more antennas,Orthogonal Frequency Division Multiplexing Access(OFDMA)and Multiple Input Multiple Output(MIMO)have been deployed in IEEE 802.11ac/IEEE 802.11 ax physical layer and improved the transmission speed to the level of Gigabit-per-Second(Gbps).For high performance WLAN baseband chips,there are many challenges from the non-ideal of analog Radio Frequency(RF)components,propagation noise and multi-path fading.Besides,the IEEE 802.11ac/IEEE 802.11 ax 4×4 chips supporting Gbps is still blank within domestic.In this thesis,two key technologies of baseband receiver,phase tracking and MIMO detection,are studied in the IEEE 802.11ac/IEEE 802.11 ax system.Novel algorithms and related architectures of the Very Large Scale Integration(VLSI)are proposed and implemented to the self-developed IEEE 802.11ac 4×4 System on Chip(SoC)and IEEE 802.11ax 2x2 SoC,supporting 80MHz bandwidth and 256QAM,with which the IEEE 802.11ac system level verification in air port is completed.The main work and innovations of the thesis are as follows.1.High performance phase tracking algorithms for VLSI implementation are proposed,including the layered phase tracking intra-symbol based on Taylor expansion and inter-symbol phase tracking based on linear filtering.For the first one,the layered model of the Carrier Frequency Offset(CFO)and the Sampling Frequency Offset(SFO)is derived from the objective function of Maximum Likelihood(ML)based on the Taylor expansion and realizes the layered estimation of CFO and SFO.With this algorithm,the interference to SFO from CFO is removed and thus the estimation of SFO is improved.Comparing to traditional Weighted Least Square(WLS)phase tracking algorithm,a better performance is achieved.Meanwhile,due to the removal of interference,calculation of weighted coefficients for SFO is simplified and the computation complexity is reduced.Furthermore,since the reference value of SFO is unchanged with different OFDM symbols,the inter-symbol phase tracking based on linear filtering is proposed and further improves the system performance.2.A low complexity VLSI architecture of phase tracking processor based on the multiplexing multiplication group is proposed.In the phase estimation module,an architecture that separates the calculation of the weighting matrix and the calculation of the CFO is designed to realize the multiplexing of the multiplication group,which reduces the number of multipliers.The results show that it can reduce the hardware resource consumption by nearly 25%.3.A MIMO detection algorithm of K-Best based on the extension of Minimum Distance Bit Flipping(MDBF)is proposed.Aiming at the Log-Likelihood Ratio(LLR)calculation of the K-Best may be invalid due to the missing bit information under the limited K condition,the nodes of each level of optimal survival path are bit flipped based on the principle of the minimum distance to obtain the missing nodes;Then iterative extension among levels is explored to obtain the missing path with lower cumulative Partial Euclidean Distance(PED).The simulation results show that it can achieve full coverage of "0" bits and "1" bits in LLR calculation,and thus increase the effective ratio of LLR calculation.With the help of proposed algorithm,the effective ratio of the first bit's LLR for 256QAM is increased from 0.2 to 0.76,which can finally significantly improve detection performance.4.A low latency VLSI architecture of MIMO detector processor based on the odd-even search level parallel processing is proposed.For the proposed MIMO detection algorithm,based on the coexistence design of full sorting and partial sorting of nodes in the existing architecture,the partial sorting of child nodes in even level and the expansion of nodes in odd level is proposed to process parallel.The results show that the processing latency can be effectively reduced by 14%.5.The phase tracking processor and MIMO detector processor proposed in this thesis are integrated into the IEEE 802.11ac 4x4 SoC supporting 80MHz bandwidth and 256QAM and its related Field Programmable Gate Array(FPGA)system is verified.The test results show that compared with the origin design,hardware resource consumption of receiver is reduced by 10%,the receiving sensitivity is improved by 1.5dB,and the throughput could reach 1.5Gbps.