Optimization Of CG Algorithm For Massive MIMO Detection And VLSI Implementation

Massive MIMO(Massive Multiple Input Multiple Output)is a key technology in next-generation wireless communications.However,with the increasing size of MIMO antenna arrays,massive MIMO systems also face many challenges.One of them is the massive MIMO detection.In uplink,massive MIMO detection faces several challenges such as high complexity and low parallelism.Linear detection algorithms,such as ZF(Zero Forcing)and MMSE(Minimum Mean Square Error),have relatively low complexity.However,due to the increasing size of massive MIMO systems,the complexity of the algorithms,including the inversion of large matrices for example,is still unacceptable.One way to solve this problem is to apply iterative algorithms to linear detection algorithms,and use iterative approaches to approximate the exact result,thereby avoiding the high complexity caused by large matrix inversions.Based on ZF,the traditional CG(Conjugate Gradient)method was optimized and the TCG(Three Term Recursion Conjugate Gradient)method was proposed.By adding parameters,the algorithm steps are changed.The data dependencies increase the parallelism of the algorithm.At the same time,a new method for initial values of iterations based on quadrants was proposed.The method determines the quadrants of the elements in the transmission vector according to the matched filter vectors,so as to reduce the Euclidean distance between the initial value and the final value of the iteration.The algorithm can converge more quickly,consequently.Based on TCG,a pipeline-based VLSI was designed to implement a 128×8 64-QAM massive MIMO detection.The VLSI architecture was verified by FPGA and the ASIC verification was achieved using TSMC's 65nm CMOS technology.Compared with the existing linear detection algorithms,besides parallelism in the computation of elements of matrices being multiplied by vectors,the TCG algorithm has more parallelism between the steps and steps of the algorithm.The new iterative initial value makes the TCG algorithm have a faster convergence speed,and can get smaller SER(Symbol Error Rate)results with fewer iterations.The iterative initial value can actually reduce the number of iterations of the algorithm,thereby reducing the complexity of the algorithm from the side.By testing the designed chip,the results show that the area of the chip is 1.87×1.87mm~2.The chip can work at a frequency of500MHz and achieve a throughput rate of 1.5Gpbs.At this time,the power of the chip is 557mW.If the preprocessing part is not considered,the energy efficiency and area efficiency of the design can reach 12.5 Mbps/mW and 3.79 Mbps/kGE,respectively.Compared with chips using CHD(Cholesky Decomposition),MPD(Message Passing Detector),and SD(Sphere Decoding),the energy efficiency of this design is improved by 4.99×,1.59×,and 13.01×,respectively,and the area efficiency is improved by 1.87×,3.59×,and 48.56×,respectively.