Research On High Performance MIMO Detector And VLSI Implementation

MIMO technology can essentially increase the channel capacity and enhance the reliability of data transmission, which is widely considered as a key technology to launch next-generation Gigabit wireless communication systems. The complexity of receiver signal detection is also increased for MIMO systems, which mean that the chip design is being more difficult. Thus, it is particularly important to design low-complexity high-performance MIMO detector with nearly maximum-likelihood (ML) performance to satisfy the requirements of modern wireless systems.This dissertation studies the high-performance detection algorithms and the hardware implementation of MIMO detector, and presents optimization and modification on MIMO detector with the consideration on algorithm, architecture and hardware implementation. The tree-search detection and lattice-reduction-aided detection are mainly discussed in this dissertation. For tree-search detection, an efficient complex-valued enumeration scheme using lookup tables is proposed, which can efficiently eliminate the problem of the nodes enumeration for complex domain K-Best algorithm. The SE K-Best algorithm presented in this dissertation has a nearly30%computational complexity reduction compared with real domain K-Best algorithm, and about20%reduction compared with previously published complex domain K-Best algorithms. For lattice-reduction-aided detection, the presented BR-CLLL algorithm in this dissertation can achieve the same performance of typical CLLL algorithm with the fixed8iteration computation, which has a32%average computational complexity reduction compared with CLLL algorithm. And a modified quantization error correction scheme is proposed, which has lower complexity and is suitable for high speed pipeline design. The lattice reduction aided LR-MMSE-SIC-QES algorithm with quantization error correction scheme can nearly achieve the ML detection performance.A configurable K-Best MIMO detector is presented in this dissertation, which is based on the above complex-valued enumeration scheme. Fabricated in TSMC65nm1P9M CMOS, the detection core circuit has75K gates, and it has about35%area reductions compare with previously published design. Operating at435MHz clock frequency, it achieves an SNR-independent throughput of1.044Gbps and consumes113pJ per bit for4×464-QAM, representing43%more energy efficient than state of the art in the previously published design.