| The main purpose of this thesis is to understand the working principle and design of an 8-port SRAM Memory cell with an emphasis to attain maximum possible Noise margin. We have proposed four designs, namely 2-SRAM, 4-SRAM, 8-SRAM, and J-SRAM capable of 8 writes or 16 reads simultaneously.; The performances of the four designs are compared with respect to noise margin. With read access time (5ns) and silicon area the same for all the designs, noise margin is measured, and it is found that J-SRAM has the maximum noise margin of 0.8251 V for a 5 V supply in an AMI 0.6mu technology. This design is also tested for read access time of 1.5ns, and the noise margin obtained is above 0.5V. If the limitation on silicon area is neglected, then a noise margin of 2V is obtained. (Abstract shortened by UMI.)... |
