Signal Integrity And Timing Analysis Of Double DDR2Interface Signal Based On Stratix IV FPGA

As is known to all, PCB layout between the MCU and DDR2is very difficult in the PCB layout design. In practical applications, the design containing double DDR2is very common. In this paper, we focus on Stratix IV FPGA of Altera and MT47H18M8DDR2of Micron, analyse the DDR2interface digital level and timing, to develop a PCB layout scheme, thus the communication between CPU and DDR2is more reliable.This paper analyzed clock signal, address/command signal, write data signal, and write data strobe signal of the DDR2interface respectively. Including all signal types of the DDR2interface. Through impedance control of the PCB transmission line, the optimization of transmission line T branch structure and the most important termination or ODT, we can implement decorate of digital waveform and adjustment of amplitude, In order to obtain the optimal level decision.On the other hand, in the clock system of double DDR2interface address/command capture and the clock signal constitute a source synchronous clock system,write data capture and write data strobe signal constitute another source synchronous clock system. But the difference between the two is, to write data capture trigger in the strobe signal upper and lower edge, and the address/command captured trigger just in the clock signal upper edge. In the respective source synchronous clock system,to make setup time margin and hold time margin maximum at the same time,namely to setup time margin equal to hold time margin. The work of this paper is to find relationships between the setup time margin/hold time margin of above systems and the signal transmission time of the the clock line, and strobe line, data and address/command line,in order,further combining the PCB transmission line delay of unit length, so we can get the relationship between time margin and length of PCB the transmission line. By adjusting the length of the transmission line, to achieve the setup time margin and hold time margin maximum.Timing simulation in the paper, using the eye measurements and eye diagram template markup. The first set the length of data lines, strobe line, clock line and address/command line respectively. By establishing the model of circuit and output eye diagram, making eye diagram template. In the eye template displays setup time, hold time, setup time margin, hold time margin and the clock jitter. Visually show the need to adjust the time margin, in order to be convenient to lines length adjustment.