Approaches for parasitic-inclusive symbolic circuit representation and extraction for synthesis

Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure, layout-aware circuit synthesis methodologies are beginning to emerge. In layout-in-the-loop synthesis methodologies, performance analysis is based on the generation of a concrete layout for the explored circuit sizes. A parasiteinclusive circuit is extracted from the layout using a standard extractor and is analyzed using a simulator to determine whether the required constraints are met. The purpose of layout generation during the synthesis process is solely to determine the layout-induced effects in terms of device and interconnect parasites in the extracted circuit in order to perform accurate, layout-aware performance analysis. If the parasites could be estimated or determined otherwise, there would be no need for layout generation. Various approaches of estimating parasitics lack the correctness that would only come from examining the layout itself.; The proposed approach tries to include the exactness of the layout to be generated without actually generating it. It relies on using pre-generated structures for the specified unsized circuit; these structures are generated before synthesis, they contain the information that a layout would have provided to a synthesis process if it was to be generated. This information contains extraction specifics for modules, location of modules and routing characteristics.; Pre-layout extraction. The concept of Pre-Layout Extraction shall be used to cover the extraction specific information of modules present in the circuit.; Multi-placement structures. For the placement specification of the layout, Multi-Placement Structures shall be used. The proposed approach aims at retaining the benefits of both optimization-based techniques and layout templates techniques: a fast instantiation time of layout for layout-inclusive synthesis and various placement possibilities for various input sizes.; Multi-variant routing. The remaining part of a layout description known as routing shall be handled using the proposed idea of Multi-Variant Routing. This method follows the same line of thought as its corresponding one in the placement field.; The combination of these three described novel methods of layout approaches can be very beneficial to the synthesis of circuits and specially analog ones. It is expected to introduce a speedup factor varying from 4 to 5 with comparison to layout-inclusive synthesis approaches while having the quality of layout exploration not found in template-based approaches. (Abstract shortened by UMI.)...