| Synthesis of analog functional blocks in integrated circuits offers promise for improved designer productivity. By developing module generators for commonly used analog circuit elements, a synthesis methodology may be matched to a particular application, with approaches and algorithms determined by the particular needs of target circuit type. An analog circuit designer should be able to input design specifications and underlying technology information, and a synthesis methodology should determine circuit parameter values and dimensions, creating the required mask layouts. Slow, tedious design and redesign methods should be replaced by one in which the computer finds minimum cost designs which meet performance requirements. This work implements synthesis methods for a widely used analog block, the digital/analog converter (DAC).;In practice, there are a number of difficult problems in synthesis methodologies. Accurate performance prediction is required, including effects of parasitic elements, and a mix of device level and circuit block level analyses. A design sizing and selection process must be determined, and methods for circuit layout must be selected.;This thesis focuses on approaches best suited to the digital/analog converter synthesis problem. A mixed analysis/simulation model for DAC behavior is developed, including an explicit inclusion of parasitic capacitive and spacing effects. A design optimization approach is developed, using a single level optimization, mixing device sizing and architecture parameters in one step. A mixed integer non-linear programming algorithm was adapted to the requirements of this optimization. Layout approaches used previously in digital datapath applications were adapted to DAC layout, producing dense layouts.;The module generation process was demonstrated through a high performance video DAC prototype, with 8-bit linearity and 100 MSample/s performance. The prototype met most performance specifications, and discrepancies between expected and observed performance were traced back to errors in the technology database input. Cell size was comparable to a manual design. The module synthesis process, including development of an initial design database, requires design time comparable to a manual approach, but subsequent reuse of the database has resulted in implementation times of a few days or even hours, thus demonstrating the ability of this combination of approaches to dramatically reduce the implementation time for high performance, digital/analog converter designs. |
