A 600 mega-sample/sec 8-bit ADC in 0.18mum CMOS

The rapid advancement of digital signal processing and the thrust to digitize analog signals at radio frequencies impose stringent requirements on high speed ADCs as a crucial component to interface between the analog and digital domains.; With the fast scaling of semiconductor technology, the lower supply voltage has become an inevitable trend for modern ULSIs. The integration of analog and digital circuits on the same chip and operating under the same supply voltage has the major advantage in reducing the overall system cost. This enforces the development of low power supply ADCs.; The main design issues for such high speed and low power supply ADCs include switching related errors, static and dynamic offsets, low dynamic range operation and difficult gain-bandwidth optimization. Design trade-offs among power, speed and chip area are further tightened with the super-scaled CMOS process.; This dissertation presents a detailed design methodology for developing a 600 Mega-Sample/Sec 8-bit ADC in CMOS, which adopts the folding and interpolation architecture to reduce the power consumption and total component number. The distributed Track/Holds (T/Hs) are applied to reduce the design constraints on individual T/H. Capacitor averaging network is uniquely embedded in distributed T/Hs to reduced the random switching errors. Boundary zero crossing shift problem in folding-interpolation network is carefully analyzed and the dummy zero crossings are applied to mitigate this problem. High efficient digital error correction logic is designed to reduce errors caused by the mismatch between the coarse and fine channels in folding ADC.; Fabricated in a 0.18mum 1P6M CMOS technology, the prototype ADC occupies an active area of 0.5 mm2. The whole ADC consumes 207mW with a single 1.8V supply while operating at 600MHz conversion rate with input signal frequencies up to 205 MHz. The measured peak DNL and INL are recorded as 0.6 LSB and 0.9 LSB, respectively. Near the Nyquist input frequencies, the SNDR always maintains above 39dB. With fixed input frequency of 55MHz, the SNDR can actually sustain at 40dB with clock frequencies up to 1GHz.