Novel low voltage power semiconductor devices and IC technologies

In recent years, low voltage (10 to 100V) power devices and power integrated circuits (PICs) based on mainstream silicon technology developed more quickly due to the rapid growth of applications in wireless communications, portable electronics, automotive, and PC peripherals, etc. In response to the increasing demands for reduced size, improved functionality, reduced cost, and energy savings of the products in these applications, low voltage power devices and PICs have to be developed correspondingly for improved radio-frequency (RF) and switching performance, improved breakdown voltage, and reduced on-resistance. Novel device structures and technology architectures are necessary in order to meet the above requirements. Microelectromechanical systems (MEMS) devices with the control circuitries integrated can provide great advantages both in improved system performance and reduced size and cost. However, the development of integrated MEMS technology is still in its early stage. The silicon-on-insulator (SOI) technology can provide low voltage RF power devices with reduced parasitic capacitances and improved RF performance, but most of the RF power devices fabricated on SOI are with a non self-aligned drift region which causes drift length variation in the different part of the device. Although there are self-aligned drift structures using a spacer approach, they require a complicated process and the drift length is limited. A low gate sheet-resistance power device is a viable way to improve the switching characteristics of the DC/DC converter. However, the conventional heavily doped polysilicon and silicide technology still provide very high sheet-resistance.; To meet the above challenges, several novel low voltage power semiconductor devices and IC technologies are proposed and demonstrated in this thesis. First, a fully integrated SOI RF MEMS technology for system-on-a-chip applications is proposed and experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip wireless communication applications. Second, a novel drift region self-aligned SOI lateral power MOSFET using a partial exposure technique is proposed and demonstrated for RF power amplifier applications. The method is simple and no additional masks are required. The drift region is self-aligned to the channel and with a length ranging from 0.3mum to as much as a few microns. Finally, a novel 30V self-aligned metal/poly-Si replacement gate planar DMOS transistor is proposed and demonstrated for high switching speed and high efficiency DC/DC converter applications. The sheet-resistance of the metal/poly-Si gate is around 0.2O/□, which is approximately 50 times lower than that of the polysilicon gate. For a device with a drain current of 69A/cm2, the turn-on and turn-off switching energy losses are reduced by 22% and 15%, respectively.