| With the development of the VLSI technology, circuits become more vulnerable to energetic radiation particles or Single Event (SE) particles. The scaled transistor dimensions, reduced power supply along with rapid signal transition times are the main reasons for circuits becoming more sensitive to these radiation particles. These factors degrade the stability of circuits and make circuits more sensitive to soft errors.;Among soft error mechanisms, this works studies the SE crosstalk delay effects and attempts to model the worst-case delays. The proposed method aims for an accurate and rapid estimation of worst case SE crosstalk delay by applying linear superposition calculation approach after linearizing the circuit. The model is verified using a 10-pi distributed interconnect model and predictive technology parameters. The model results are very close to HSPICE simulation results while allowing for accurate and time-efficient worst-case delay analysis. |
