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Delay Modeling For Wide Voltage Range Circuits Based On Substitution Model

Posted on:2022-05-18Degree:MasterType:Thesis
Country:ChinaCandidate:C Z XuanFull Text:PDF
GTID:2518306740990579Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Wide-voltage design broadens the working scenarios of chips and optimizes the energy efficiency.At the same time,circuit delay analysis receives great challenges.Delay modeling and timing yield analysis for wide-voltage circuits are heavy non-Gaussian and nonlinear problems.The delay distribution will degenerate from Gaussian to heavy-tail as the voltage decreases.The main difficulties of the problem are how to accurately estimate the parameters of the heavy-tail distribution and estimate the timing yield through integration.This thesis proposes a wide voltage range circuit delay model based on the surrogate models to estimate time delay yield,instead of the high cost of transistor level simulation.In addition,this model generates a high precision delay distribution to guide design optimization.Firstly,the Low-Rank Tensor Approximation(LRTA)is used to simulate the delay changes from a large number of process parameters fluctuations.As a substitution model with adjustable precision,LRTA model adjusts the number of coefficients along with voltage change in order to use minimum cost to fit the complex mapping relationship between delay time and process parameters.Secendly,an adaptive nonlinear sampling algorithm is adopted to generate new sample points to iteratively calibrate the model,which ensures the rapid convergence of the model.The sampling method focuses on the mapping function's non-linear region,which increases the sampling weight near the failure boundary to ensure new samples gather in the failure boundary and the heavy non-linear region.These samples carry more information,and the sampling efficiency is improved as a result.Finally,for high-dimensional circuits,Slice Inverse Regression(SIR)is used to reduce the dimension of input parameters,simplify model parameters and accelerate convergence.In this thesis,the 45 nm Free PDK TAU15 benchmark and the 28 nm TSMC ISCAS'85benchmark are studied in experiment.The Log Skew Normal distribution(LSN)and Maximum Entropy estimation(MAXENT)are reference objects.The results show that,the proposed method achieves 20?100 times(45nm)and 20.8?333.3 times(28nm)speedup compared to the Monte Carlo simulation with basically the same accuracy for delay distribution parameters and yield estimation.
Keywords/Search Tags:delay model, timing yield, wide-voltage range, non-Gaussian, non-linear sampling
PDF Full Text Request
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